1. Field of the Invention
The present invention relates to a data converter, and more particularly, an analog to digital data converter using active interpolation to realize background auto-zeroing.
2. Description of the Prior Art
Using digital signals for information transmitting, processing and storing is an important foundation of the information industry. A digital signal is basically composed of a high state and a low state, so the digital signal has a high noise tolerance. In addition, the digital signals can be processed in a modular design. Therefore, circuits for transmitting, processing, and storing digital signals are key issues in the information industry.
All signals are essentially analog signals that vary continuously, such as human voices, natural light, and so on. A data converter, which can convert analog data to digital, is needed for processing analog signals into digital form. Digital signals are really continuous analog signals. In a digital signal, while the waveform of the signal varies, for instance from a high state to a low state, a transient state exists. The transient state comprises a rising edge and a falling edge. Thus, the waveform of the digital signal is not a perfect square wave. Digital signals are less ideal when the digital signals are frequently switched between different states. For processing the non-ideal digital signals, an analog to digital data converter is needed to obtain digital signals with more ideal characteristics. For this purpose, data converters must operate rapidly and continuously to obtain high frequency digital signals in real time.
Please refer to FIG. 1 of a schematic diagram of a prior art data converter 10, which is used to convert an analog input signal Vin to a corresponding digital signal. The data converter 10 comprises a voltage dividing circuit 12, an encoding circuit 16, and a plurality of comparison units 14. In FIG. 1, eight comparison units are shown by way of example. The voltage dividing circuit 12 comprises a plurality of resistors such as Ra, Rb, and Rc for dividing a voltage Vdc into different reference voltages Vr1 to Vr8 respectively at each node. Bach of the comparison units 14 comprises an amplifier 18 and a latch circuit 19. The amplifier 18 receives the reference voltage generated by the voltage dividing circuit 12, and an input signal Via for amplifying the difference between these two input signals to generate a corresponding signal to the latch circuit 19. The latch circuit 19 is triggered by a clock vclock to convert the output signal of the amplifier 18 to a digital signal in a high or low state. This converted digital signal is output to the encoding circuit 16. The encoding circuit 16 processes (for example, corrects) and encodes the digital signals generated by the comparison units 14.
Please refer to FIG. 2 of a timing diagram of the clock vclock, the input signals Vin, and the output digital signals of each comparison unit while the prior art data converter 10 operates. The transverse axis in FIG. 2 is time. When the analog input signal Vin reaches the data converter 10. the amplifier 18 compares the input signal Vin with the corresponding reference voltage and outputs a comparison result to the latch circuit 19. According to the comparison result and a trigger of the clock vclock, the latch circuit 19 outputs a digital signal in a high state, which is shown by 1, or a low state, which is shown by 0. For example, at time t1, if the input signal yin is less than the reference voltages Vr1 and Vr2 but more than the reference voltages Vr3 to Vr8, then the latch circuit 19 is triggered by the negative edge of the clock vclock (which is shown by arrows) and outputs digital signals as 0, 0, 1, 1, 1, 1, 1, and 1. In this manner, the input signal Via at time t1 can be converted to a digital signal (0, 0, 1, 1, 1, 1, 1, 1). The encoding circuit 16 can encode the digital signal in advance, such as 011.
For the purpose of converting input analog signals to digital signals correctly, each amplifier must respond to the relationship between the input signal Vin and the reference voltage correctly. In a real circuit, each comparison unit generates an offset voltage due to the non-ideal characteristics of the device. This means the comparison unit adds the offset voltage to the input signal Vin and then compares the modified input signal Vin with the reference voltage. Thus, the comparison is not performed in an ideal operation situation. Additionally, if each comparison unit has different offset voltages, the data converter 10 is affected, and converts signals incorrectly.
To adjust for the offset voltage in the comparison units, an auto-zeroing process is used to solve the problem. Please refer to FIG. 3 of a schematic diagram of a data converter 20 in the prior art. The data convener comprises a voltage dividing circuit 22 for providing reference voltages Vr1 to Vr4, four comparison units 24A to 24D, auxiliary circuits 26A and 26B, and an encoding circuit 28. The comparison units 24A to 24D have the same structure. The comparison unit 24A comprises four switches SP1, SP2, SP3 and SP4, a differential amplifier Ka with one output end and two input ends, a capacitor C0, and a latch circuit Ja. The switches SP1 to SF4 are controlled by a control signal Vc1 and an inverted signal of the control signal vc1 shown as{overscore (vc1)}The amplifier Ka comprises a feedback circuit controlled by the switch SP3 electrically connected to the input end P11 and the output end P12. The other input end of the amplifier Ka is electrically connected to a common mode voltage V0. The latch circuit Ja is triggered by the clock vclock. Each comparison unit is electrically connected to a resistor Rc.
The data converter 20 operates as follows. The amplifier compares the input signal Vin with the reference voltage and outputs the comparison result to the latch circuit. The latch circuit is then triggered by the clock vclock to generate a digital signal. To compensate for the offset voltage generated in the amplifiers, the switches in each comparison unit conduct or open to allow each comparison unit to perform a comparing process or, alternatively, an auto-zeroing process. The comparison unit 24C shown in FIG. 3 is in the auto-zeroing process. Please notice that the switches in the comparison unit 24C can conduct the feedback circuit of the amplifier Kc, and the capacitor can be also electrically connected to a corresponding reference voltage Vr3. At this time, the reference voltage Vr3 charges the capacitor C0 via the switch SP2 in the comparison unit 24C. When the feedback circuit conducts, a closed loop is formed at the node P31 so that the amplifier Kc is virtually grounded to the common mode voltage V0. Thus, the charge amount in the capacitor C0 is dependent on the reference voltage Vr3. The charge amount is enough to compensate for the offset voltage of the amplifier Kc, and the goal of auto-zeroing is achieved.
After the auto-zeroing process, each comparison unit switches to a comparing process and compares the input signal with the reference voltage. Then, a corresponding digital signal is output from the latch circuit. For example, the comparison unit 24A shown in FIG. 3 is performing a comparison process. Please notice that the switch SP3 is opened so that the feedback circuit does not conduct and place the amplifier Ka in an open loop. The signal Vin is input to the capacitor C0 via the switch SP1 so that voltages on both terminals of the capacitor C0 are modified. Since the charge amount of the capacitor C0 in the auto-zeroing process corresponds to the reference voltage, the voltage on node P11 corresponds to a comparison result between the input signal Vin and the reference voltage. This comparison result is sent to node P12 by the amplifier Ka. Finally, the comparison result is output to the latch circuit Ja via the switch SP4 and converted to a digital signal according to the trigger of the clock vclock. Thus, the purpose of comparing the input signal Vin and the reference voltage, and converting the input signal Vin, is achieved.
Next, please refer to FIG. 4 of a timing diagram of the control signals vc1 to vc4 and the clock vclock in the comparison units of the data converter 20. The transverse axis in FIG. 4 is time. Among the control signals vc1 to vc4, the signals in the high state control corresponding switches to conduct, and the signals in the low state control corresponding switches to open. The negative edge of the clock vclock triggers the latch circuit to latch digital signals. At time T2, the control signal vc3, which is in the high state, controls all switches in the comparison unit 24C to keep the comparison unit 24C in an auto-zeroing process during period Tz. At this time, the control signals vc1, vc2 and vc4, which are in the low state, keep the comparison units 24A, 24B, and 24D in the comparing processes respectively. Thus, the input signal Vin is compared with the reference voltage in each comparison unit and converted to a digital signal.
At time t2, the data converter 20 has only three comparison units performing the comparing process. The comparison unit 24C performs the auto-zeroing process and therefore no comparison result is available. However, the comparison unit 24B is electrically connected to the comparison unit 24D via the resistor Rc. A comparison result for the comparison unit 24C in the auto-zeroing process is generated by an interpolation method. The theory of the interpolation method is illustrated in FIG. 5 of a schematic diagram of converting curves of amplifiers K1 in the comparison units 24B to 24D. The transverse axis in FIG. 5 is the input voltage of the amplifier K1 that is differentially input. The longitudinal axis is the output voltage of the amplifier K1. The converting curves TP2 to TP4 correspond to the amplifier in the comparison units 24B to 24D respectively. The voltage Vk is a standard voltage for a latch circuit K2 to output a high or low digital signal. That means if the output voltage of the amplifier is higher or lower than the standard voltage Vk, the corresponding latch circuit generates a digital signal in a high or low state.
As shown in FIG. 3, when the comparison unit 24C is in the auto-zeroing process, the input of the latch circuit Jc, which is the voltage at the node P33, is dependent on the outputs of the amplifier Kb and Kd. When the comparison unit 24C performs the auto-zeroing process, the voltage of the comparison unit 24C is the interpolated value of the output voltages of the amplifiers Kb and Kd. Thus, the voltage characteristic at node P33 is an average of the converting curves TP2 and TP4 along the longitudinal axis in FIG. 5. Using the average of the converting curves TP2 and TP4 to obtain another converting curve TP3z is shown by arrow 27. If the converting curves TP2 and TP4 of the amplifiers Kb and Kd are both approximately linear and the reference voltage Vr3 is designated as an average value of the reference voltages Vr2 and Vr4, the average converting curve TP3z intersects the output voltage Vk on the longitudinal axis at the reference voltage Vr3 on the transverse axis.
As described above, when the comparison unit 24C performs the auto-zeroing process, the converting curve TP3 of the amplifier Kc is replaced by the converting curve TP3z that is obtained from the amplifiers Kb and Kd. The converting curve TP3z is not equal to the converting curve TP3. However, if the converting curve TP3z and the voltage Vk on the longitudinal axis intersect at the reference voltage Vr3 on the transverse axis, the converting curve TP3z at the node P33 can drive the latch circuit Jc. That means if the voltage at the node P33 is higher or lower than the standard voltage Vk, the corresponding latch circuit generates a digital signal in a high or low state respectively. Although the comparison unit 24C in the auto-zeroing process does not compare the input signal Vin with the reference voltage at the same time, a comparison result can be obtained by the interpolation of the adjacent comparison units.
As shown in FIG. 4, the data converter 20 has only one comparison unit in the auto-zeroing process at any time. The two adjacent comparison units, via the resistor network that is composed of the resistor Rc, interpolate the comparison result of the comparison unit in the auto-zeroing process. If the comparison unit 24A or 24D perform the auto-zeroing process, the comparison result is interpolated by the auxiliary circuits 26A or 26B and the comparison unit 24B or 24C.
While the data converter 20 converts analog signals to digital signals, each comparison unit performs the auto-zeroing process in turn. While one comparison unit is in the auto-zeroing process, its comparison result comes from other comparison units by an interpolating method via the resistor network, so that the data converter 20 operates with full functionality. However, a transient effect happens while the resistor network interacts with the capacitors in the data converter 20. When the comparison units generate a replacement comparison result via the resistor network, signals are delayed due to the RC constant so that the input bandwidth of the conventional data converter 20 is limited. The resistor network of the resistor Rc also increases the complexity and costs of circuit design and manufacture.
Additionally, the converting curve of each amplifier must have a large linear range so that the converting curve can be interpolated correctly. As shown in FIG. 5, the converting curve TP2 and TP4 near the reference voltage Vr3 had better be linear so that the converting curve TP3z, which intersects with the voltage Vk at the reference voltage Vr3, can be averaged correctly. If the converting curves TP2 and TP4 near the reference voltage Vr3 are not linear, the curve TP3z will incorrectly replace the converting curve TP3. As known, the above paragraph is suitable for some special cases, for example, 2X interpolation. In other cases, the amplifier need not be linear near Vr3. The accuracy of the interpolated Vr3 depends on the odd symmetry of the I/O characteristics of the amplifier. The comparison units also perform the auto-zeroing process one by one, and thus different control signals for each comparison unit are required. For instance, four control signals are required for the four comparison units shown in FIG. 4. The resulting circuit design is complicated.